Multi-level integrated circuit (IC) manufacturing requires many steps of metal and insulator film depositions followed by photoresist patterning and etching or other means of material removal. After photolithography and etching, the resulting wafer or substrate surface is non-planar and contains many features such as vias, lines or channels. Often, these features need to be filled with a specific material such as a metal or other conductor. Once filled with a conductor, the features provide the means to electrically interconnect various parts of the IC.
Electrodeposition is a technique used in IC manufacturing for the deposition of a highly conductive material, such as copper (Cu), into the features on the semiconductor wafer surface. FIG. 1 is a schematic illustration of a wafer or substrate 16 to be coated with Cu. Features 1 may be vias, trenches, bond pads, etc., and are opened in the dielectric or insulator layer 2. To achieve Cu deposition, a barrier layer 3 is first deposited over the whole wafer surface. Then, a conductive Cu seed layer 4 is deposited over the barrier layer 3. An electrical contact is made to the barrier layer 3 and/or the seed layer 4, the wafer surface is exposed to a Cu plating electrolyte, and a cathodic voltage is applied to the wafer surface with respect to an anode which also makes physical contact with the electrolyte. In this way, Cu is plated out of the electrolyte, onto the wafer surface, and into the features 1.
The terms “wafer” and “substrate” are used interchangeably above and throughout the remaining description. Referring to the example shown in FIG. 1, it is to be understood that the “wafer” or “substrate” referred to includes the wafer WF per se, the dielectric or insulator layer 2, and the barrier layer 3, with or without the seed layer 4. These terms, of course, may also refer to a wafer WF per se, including one or more previously processed layers, a further dielectric or insulator layer, and a further barrier layer, with or without a further seed layer.
The electrical contact to the seed layer and/or the barrier layer is typically made along the periphery of the wafer, which is usually round. This approach works well for thick and highly conductive seed layers and small wafer diameters (e.g. 200 mm). However, the trend in the semiconductor industry is to go to larger wafers (e.g. 300 mm) and smaller feature sizes (smaller than 0.18 microns). Smaller feature sizes, as well as cost considerations, require the use of the thinnest possible seed layers. As the wafer size increases, the plating current value also increases. As the seed layer thickness decreases, the sheet resistance increases, and the voltage drop between the middle and the edge of a large wafer also increases. Therefore, voltage drop becomes a major problem, especially for large wafers with thin seed layers. This voltage drop results in non-uniform Cu deposition on the wafer surface, the regions near the contacts being typically thicker than other regions.
One other consideration in Cu plating is the “edge exclusion”. Cu plating heads, such as the one described in commonly assigned, copending application Ser. No. 09/472,523, filed Dec. 27, 1999, titled WORK PIECE CARRIER HEAD FOR PLATING AND POLISHING, typically use contacts around peripheries of the wafers. Making electrical contact and, at the same time, providing a seal against possible electrolyte leakage is difficult.
FIG. 1a shows a cross sectional view of a contacting scheme in which the wafer or substrate 16 is contacted by a ring-shaped contact 17 which is sealed by a ring seal 18 against exposure to the electrolyte 9a. The seal 18 also prevents the electrolyte 9a from reaching the back surface of the wafer or substrate 16. Such a contacting scheme extends a distance “W” from the edge of the wafer. The distance “W” is referred to as “edge exclusion” and may typically be 3-7 mm. Minimizing “W” would allow better utilization of the wafer surface for IC fabrication.
There is, therefore, a need to develop new and novel approaches to provide electrical contacts to the surface of semiconductor wafers during electrodeposition of conductors.